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MRF89XA
FIGURE 3-22:
TX PROCESSING IN BUFFERED MODE (FSIZE = 16, TXSTIRQ0 = 0))
Start condition
IRQ0TXST
FIFOFULL
FIFOEMPTY
TXDONE
from
SPI Data
15
FIFO
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Data TX
(from SR)
XXX
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10 b11 b12 b13 b14 b15
XXX
3.10.2
RX PROCESSING
The host microcontroller software must therefore
After entering RX in Buffered mode, the MRF89XA
requires the host microcontroller to get received data
from the FIFO. The FIFO will start being filled with
received bytes either when a Sync word has been
detected (in this case only the bytes following the Sync
word are filled into the FIFO) or when the FIFOFSC bit
(FPPRIREG<6>) is issued by the user depending on
the state of bit, FIFOFM (FTPRIREG<7>).
In Buffered mode, the packet length is not limited that
is, as long as FIFOFSC is set the received bytes are
shifted into the FIFO.
manage the transfer of the FIFO contents by interrupt
and ensure reception of the correct number of bytes. In
this mode, even if the remote transmitter has stopped,
the demodulator will output random bits due to noise.
When the FIFO is full, the FIFOFULL IRQ (source) is
issued to alert the host microcontroller that at that time,
the FIFO can still be unfilled without data loss. If the
FIFO is not unfilled, after the SR is full (that is, 8 bits
periods later) FOVRRUN is asserted and the SR’s con-
tent is lost.
Figure 3-23 illustrates RX processing with a 16 byte
FIFO size and FIFOFSC = 0 . Note that in the example
of Section 3.10.5, Buffered Mode Example , the host
microcontroller does not retrieve any bytes from the
FIFO through SPI data interface, causing an overrun.
FIGURE 3-23:
RX PROCESSING IN BUFFERED MODE (FSIZE = 16, FIFOFM = 0)
Data RX
(to SR)
“noisy” data
Preamble
Sync
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10 b11 b12 b13 b14 b15 b16
Start condition
(FIFOFM)
FIFOEMPTY
FIFOFULL
FOVRRUN
WRITEBYTE
15
FIFO
0
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
DS70622C-page 78
Preliminary
? 2010–2011 Microchip Technology Inc.
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